A. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular to a method of manufacturing a power semiconductor element, a type of a semiconductor device, which has electrodes on the front surface side and the rear surface side, and a plating layer formed on the electrode on the front surface side.
B. Description of the Related Art
Power semiconductor devices generally used in power conversion apparatuses include the semiconductor elements that perform a switching operation such as power MOSFETs (metal oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors), and the FWD (free wheeling diode) used in combination with those elements.
The IGBT is a power semiconductor element that exhibits a high speed switching characteristic and a voltage-driving characteristic, which are possessed by a MOSFET, and a low on-voltage characteristic possessed by a bipolar transistor.
In the following description, a semiconductor region prefixed by “n” or “p” is a region in which the majority carrier is an electron or a positive hole, respectively. The sign “+” or “−” added to the symbols n and p such as n+ or n− means that the impurity concentration of a region with the sign is larger or smaller, respectively, than that of a region without the sign.
There are three types of structures of an IGBT: a punch-through type (abbreviated to a “PT” type in the following description), a non-punch-through type (abbreviated to a “NPT” type in the following description), and a field-stopping type (abbreviated to an “FS” type in the following description). A PT type IGBT uses an epitaxial substrate having an n+ buffer layer and an n− active layer, each being epitaxially grown on the surface of a p+ semiconductor substrate. A power semiconductor element of an IGBT for a withstand voltage of 600 V class has an active layer with a thickness of about 100 μm and a total thickness including a p+semiconductor substrate in the range of 200 μm to 300 μm. The PT type IGBTs, which are manufactured using an epitaxial substrate, are expensive.
Another method is known for manufacturing an NPT type IGBT and an FS type IGBT to use a floating zone substrate (abbreviated to an “FZ” substrate in the following description). The FZ substrate is cut out from a semiconductor ingot manufactured by a floating zone method. These types of IGBTs have a shallow p+ collector layer formed in the rear surface side of the substrate with a low dose.
Next, a structure of an NPT type IGBT is described. FIG. 5 is a sectional view showing a structure of an NPT type IGBT, which is manufactured using an FZ substrate. Referring to FIG. 5, the reference numeral 1 designates an n-type FZ substrate, which is an n− drift layer. The n− drift layer works as an active layer. The reference numeral 2 designates a p+ base region, the numeral 3 designates an n+ emitter region, 4 a gate oxide film, 5 a gate electrode, 6 an emitter electrode, and the reference numeral 7 designates an interlayer insulation film.
The p+ base region 2 is selectively provided in the surface region of n− drift layer (FZ substrate) 1. N+ emitter region 3 is selectively provided in the surface region of the p+ base region 2.
The side of FZ substrate 1 in which n+ emitter region 3 is provided is defined as a front surface side of FZ substrate 1. On the surface of the front surface side of substrate 1, gate electrode 5 is provided through underlying gate oxide film 4. On gate electrode 5, interlayer insulation film 7 is provided. Emitter electrode 6 is provided in contact with p+ base region 2 and n+ emitter region 3 and insulated from the gate electrode by interlayer insulation film 7.
A surface opposite to the front surface of FZ substrate 1 is the rear surface. On the rear surface of FZ substrate 1, p+ collector layer 8 and collector electrode 9 are provided.
Next, a structure of an FS type IGBT is described. FIG. 6 is a sectional view showing a structure of an FS type IGBT, which is again manufactured using an FZ substrate as the device of FIG. 5.
Referring to FIG. 6, the reference numeral 1 designates the n type FZ substrate, which is an n− drift layer. The n− drift layer works as an active layer. The reference numeral 2 designates a p+ base region, the numeral 3 an n+ emitter region, 4 a gate oxide film, 5 a gate electrode, 6 an emitter electrode, and 7 an interlayer insulation film. Relative positions among these parts are similar to those in FIG. 5 and description is omitted.
FIG. 6 is different from FIG. 5 in that an n buffer layer 10 is provided between n− drift layer 1 (FZ substrate) and p+ collector layer 8 in the rear surface region of FZ substrate 1.
The NPT type IGBT and the FS type IGBT, which are manufactured using FZ substrate 1, have a total thickness greatly reduced from that of the PT type IGBT. Specifically, an FS type IGBT has a total thickness in the range of 80 μm to 200 μm.
A power semiconductor element for a withstand voltage of 600 V class, for example, has a total thickness of the FZ substrate 1 of about 100 μm. Since the injection rate of positive holes can be controlled, high speed switching is performed without lifetime control. Power semiconductor elements that use an FZ substrate, which is inexpensive as compared with an epitaxial substrate, can be provided more cheaply than power semiconductor elements that use an epitaxial substrate.
Now, a method of manufacturing an FS type IGBT is described. FIG. 7 is a flow chart showing steps of a method of manufacturing an FS type IGBT.
First in step S301, the parts in the front surface side of FZ substrate 1 shown in FIG. 6 are formed including p+ base region 2, n+ emitter region 3, gate oxide film 4, gate electrode 5, emitter electrode 6, and interlayer insulation film 7. The structure inclusive of all these parts is referred to as a front surface structure.
Then, in step S302, the rear surfaced side of FZ substrate 1 is ground (back-grinding) to reduce a thickness of FZ substrate 1. For example, FZ substrate 1 with a thickness of 600 μm is ground to about 120 μm. In order to eliminate the damage on the substrate surface such as strain caused by the grinding process, the rear surface side of FZ substrate 1 is removed by an etching process. The etching process removes 20 μm, for example. Although the etching process can be carried out by either wet etching or dry etching, a wet etching process is conducted in this example in step S303.
On the rear surface side of FZ substrate 1, which has been cleaned after completion of the etching process, two types of ions are successively injected (ion-implantation) in step S304. After the ion-implantation, an activating heat treatment is conducted to form n buffer layer 10 and p+ collector layer 8 in step S305.
Then, collector electrode 9 is formed in step S307 on the surface of p+ collector layer 8 by laminating a metal by means of an evaporation method or a sputtering method. The metallic layer laminated on the surface of p+ collector layer 8 is, for example, a lamination of aluminum, titanium, nickel, and gold deposited in this order. Prior to laminating the metallic layer, it is preferable to remove a natural oxide film formed on the surface layer of p+ collector layer 8 using dilute hydrofluoric acid in step S306.
An aluminum layer in the metallic layer is preferably composed of an aluminum-silicon layer containing silicon with a content in the range from 0.5 wt % to 2 wt %, more preferably at most 1 wt %.
This material is used in order to avoid aluminum spike. The aluminum spike is formed in the process of forming an aluminum layer or in heat treatment process after forming the aluminum layer, in which aluminum penetrates from the aluminum layer into the underlying semiconductor substrate of silicon. If this aluminum spike pierces through the pn junction between n buffer layer 10 and p+ collector layer 8 in the rear surface side of an FS type IGBT, degradation of electric performance, for example increase in leakage current is caused in the FS type IGBT.
An aluminum layer composed of an aluminum-silicon layer containing silicon prevents the aluminum spike from extending into the underlying semiconductor substrate. The titanium layer prevents nickel of the upper layer from diffusing into the aluminum layer that is an aluminum-silicon layer. The nickel layer is provided for solder joining to an external terminal (not shown in FIG. 6). The gold layer on the nickel layer inhibits oxidation of the nickel layer.
When a chip of a power semiconductor device is packaged, the chip is connected to a circuit pattern and conductor strips (hereinafter, generally referred to as external terminals) on an insulation board. For example, a collector electrode in the rear surface side of a power semiconductor element is connected to an external terminal by solder joining and an emitter electrode in the front surface side is connected to an external terminal by wire bonding using an aluminum wire in conventional technologies.
In order to achieve high density packaging of a module package, enhancement of current density, reduction of wiring capacitance for high speed switching, and improvement in cooling efficiency of a semiconductor element, a method of joining electrodes on the front surfaced side to external terminals by solder joining has been proposed.
Use of the solder joining for connection between a power semiconductor element and external terminals in place of the wire-bonding obviates a space required by distribution wires in the wire-bonding to minimize the volume of the module package. In addition, a wiring capacitance of a connection part between the power semiconductor element and the external terminals is also minimized. While an electric current fed in a bonding wire in the wire-bonding is restricted because of an electric resistance in the bonding wire, the solder joining can enhance the current density. Moreover, the external terminal (for example, a copper plate) can be directly cooled with cooling water, greatly improving cooling efficiency of the semiconductor element.
In order to perform the solder joining between the electrode on the front surface side of the power semiconductor element and the external terminal, it is necessary to provide it with a metallic layer (of nickel, for example) exhibiting a good wettability on the surface of the electrode on the front surface side. Japanese Unexamined Patent Application Publication No. 2005-019798 discloses formation of a metallic layer with good wettability by means of a plating method.
A technique of electroless plating can be employed for forming a plating of the metallic layer on the front surface side of the semiconductor substrate in a step of manufacturing a power semiconductor element. In the electroless plating, if a part of the surface of the semiconductor substrate is exposed at a dicing line for cutting the semiconductor substrate into individual pieces of power semiconductor elements, a plating layer grows on the surface of the dicing line, which is at an equal potential to the front surface side of the substrate. A plating layer also grows on the outer periphery of the semiconductor wafer on which no power semiconductor element is formed. There is further possibility of plating layer growth even on the rear surface side of the semiconductor substrate. A plating layer formed on the peripheral region or on the rear surface of the semiconductor substrate causes a problem of non-uniformity of the plating layer formed on the front surface side of the semiconductor substrate.
In order to suppress the non-uniformity, Japanese Unexamined Patent Application Publication No. 2006-156772 and Japanese Patent No. 3831846 disclose a technique to cover the dicing line and the peripheral face of the semiconductor substrate with an insulation film or a resin. However, even when the dicing line on the front surface side and the peripheral side face of the semiconductor substrate are covered with the insulation film or the resin, there is still the possibility of plating on the rear surface side of the semiconductor substrate, which is not activated for the electroless plating liquid. This plating can occur from nuclei of residue of zinc that remains due to insufficient cleaning after zinc substitution treatment in a double zincate treatment, which is a preliminary treatment for the electroless nickel plating. The suspension in the electroless plating liquid can also be the nucleus for this undesired plating.
The abnormal plating layer of nickel, for example, deposited on unintended places may occasionally be peeled off from the electrode on the rear surfaced side of the semiconductor substrate and falls down into the electroless plating liquid by oscillation of the substrate in the electroless plating liquid. Each fallen nickel piece becomes a nucleus to initiate continuing precipitation of nickel in the plating bath, which decreases the nickel concentration in the plating bath.
In the electroless plating, a treatment time for obtaining a desired thickness of the plating layer is determined based on a preliminarily measured deposition rate. If the concentration in the plating liquid changes, the deposition rate of the plating layer changes as well. As a result, the pre-determined treatment time is insufficient for obtaining a plating layer with the desired thickness. Therefore, when the nickel has fallen down into the plating liquid, it becomes necessary to wash the plating bath and replace the plating liquid.
In order to cope with this problem and to carry out plating exclusively on the front surface side of the semiconductor element, a technique has been proposed in which a dedicated jig is used which has a structure to prevent the plating liquid from circulating behind the rear surface side of the semiconductor substrate, and the substrate is fastened with the jig. Another method has been proposed in which a resist is applied on the places where the plating is not to be formed, such as the rear surface and the side plane of the semiconductor substrate. The electroless plating is conducted after forming a protective film of the resist.
Japanese Unexamined Patent Application Publication No. 2005-191550 and Japanese Unexamined Patent Application Publication No. 2007-317964 disclose a technique in which an adhesive liquid is spread onto a surface of the semiconductor substrate opposite to the surface of treatment and is preliminarily dried for reducing flowability, thus maintaining the shape as an adhesive layer. Then, a support plate is stuck to the adhesive layer.
Japanese Unexamined Patent Application Publication No. 2003-173993 discloses another method which uses a support plate for protecting a semiconductor wafer. The support plate is stuck on the wafer with a tape for protecting a surface of the semiconductor wafer opposite to the surface to be treated. The tape has an adhesive material layer that is formed on one surface of the base material of the tape and contains a gas-generating agent that generates a gas on receiving light.
Japanese Unexamined Patent Application Publication No. 2004-064040 discloses still another method in which a joining layer is formed on the surface of the semiconductor wafer opposite to the surface to be treated. Then, the semiconductor wafer is stuck, with the joining layer, to a light transmissive support such as a glass plate that has a photo-thermal conversion layer containing a light absorber and a thermally decomposable resin.
However, a semiconductor substrate having a thickness as thin as in the range of 80 μm to 200 μm has been warped through the prior steps. When the semiconductor substrate is fastened interleaved between a dedicated jig having a structure for preventing the plating liquid from circulating around the rear surface side of the substrate, such a thin warped semiconductor substrate may be broken or chipped in the process of interleaving and fastening between the dedicated jig. Consequently, the manipulation of interleaving can hardly automated and a hand work by a worker is necessary. Thus, the method requires much time and labor, and is not suited for mass production.
In the method of applying a resist for a protective film mentioned earlier, the adhesiveness between the resist and a metal layer for an electrode already formed on the rear side surface of the semiconductor substrate is low. As a result, the resist peels off from the semiconductor substrate in the electroless nickel plating process, which is conducted at a temperature around 80° C. In addition, an organic solvent component in the resist dissolves in the plating liquid, contaminating the plating liquid. The contamination of the plating liquid with an organic solvent causes poor adhesion between the plating layer and an underlying layer, swelling of the plating layer, little precipitation of the plating layer, slow rate of precipitation, uneven luster and cloudiness on the plating surface, and abnormal precipitation of the plating. Therefore, the contaminated plating liquid needs to be replaced and the plating bath must be washed. Since the resist is expensive, the manufacturing cost of a power semiconductor element increases. Moreover, a thin semiconductor substrate having a thickness at most 200 μm, when the protective film is formed with a resist, warps due to stress generated in the process of curing the resist, causing difficulty in automated transportation of the semiconductor substrate.
The above-described problems exist not only in the electroless nickel plating, but also in the plating of other metals such as gold plating.
There is a problem described below in the method in which an adhesive liquid is spread onto a surface of a semiconductor substrate opposite to the surface of treatment and is preliminarily dried to reduce flowability while maintaining the shape as an adhesive layer followed by sticking of a support plate to the substrate surface. Since the adhesive layer in this method needs to be dissolved with alcohol in the step for peeling off the support plate from the semiconductor substrate, the support plate has a multiple of small holes across the plate from the non-adhering surface to the adhering surface formed over the entire surface thereof. If this structure is applied to electroless plating, where a solution of a strong acid of nitric acid or a strong alkali of sodium hydroxide is used, this agent reaches the adhesive layer through the multiple of holes. The adhesive layer touched the agent dissolves and loses its adhesivity causing peel off of the support plate, and further the plating liquid is contaminated.
There is a problem described below in the method for protecting the rear surface of a semiconductor substrate by sticking a support plate on the rear surface of the substrate using a tape stuck on the surface of the substrate opposite to the surface to be treated. The tape has adhesive material layers formed on both surfaces of the base material thereof. One of the two adhesive material layers that is to be stuck on the substrate contains a gas generating agent to generate a gas upon receiving light. When the tape containing a gas generating agent, is used with the support plate stuck thereon and is immersed in the plating bath for electroless nickel plating or electroless gold plating with a plating liquid at a temperature in the range of 70° C. to 90° C., the gas generating agent generates a gas responding to the temperature in the plating process and the support plate is peeled off.
There is a problem described below in the method for protecting a rear surface of a semiconductor substrate by forming a joining layer on the surface of the semiconductor substrate opposite to the surface to be treated and sticking a light transmissive support to the substrate through the joining layer. In order to peel off the light transmissive support from the joining layer, an adhering surface of the light transmissive support is provided with a photo-thermal conversion layer preliminarily formed thereon, the photo-thermal conversion layer containing a light absorber and a thermally decomposable resin. Glass is used for the light transmissive support. In this method, the light transmissive support is expensive; the cost for forming the photo-thermal conversion layer on the glass is high; and when the light transmissive support is recycled, the cost for cleaning the decomposed photo-thermal conversion layer is high. Thus, a manufacturing cost employing the method is expensive on the whole. Moreover, the joining layer remained on the semiconductor substrate must be peeled off with a peeling tape or the like in an additional process after peeling off the light transmissive substrate.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.